Design flow integration and automation with Magia

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License: MIT License, Other/Proprietary License (LICENSE)

Author: khwong-c64

Tags Verilog HDL, SystemVerilog, Synthesizable, RTL, HDL, Hardware Description Language, Code Generation, FPGA, ASIC, EDA, RTL Design

Requires: Python >=3.9, <4.0

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Project description

Magia Flow

Brief

Design flow integration and automation with Magia.

Project Roadmap

TBD

Installation

pip install magia-flow

Examples

TBD

Documentation

TBD

Contributing

We also have a Contribution Guideline and Code of Conduct. Please take a look before you contribute.

In case you are interested in this project, contact me via: https://github.com/khwong-c

Reference

TBD

Project details

Verified details

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Avatar for khwong-c from gravatar.com khwong-c

Unverified details

These details have not been verified by PyPI
Project links
GitHub Statistics

View statistics for this project via Libraries.io, or by using our public dataset on Google BigQuery

Meta

License: MIT License, Other/Proprietary License (LICENSE)

Author: khwong-c64

Tags Verilog HDL, SystemVerilog, Synthesizable, RTL, HDL, Hardware Description Language, Code Generation, FPGA, ASIC, EDA, RTL Design

Requires: Python >=3.9, <4.0

Classifiers

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This version

0.1.0

0.0.1

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