An open-source HDL register interface code generator fast enough to run in real time
Project description
The hdl-registers project is an open-source HDL register interface code generator fast enough to run in real time. It makes FPGA/ASIC development more fun by automating a lot of time-consuming manual work. It also minimizes the risk of bugs by removing the need for duplicate information. Read more
See documentation on the website: https://hdl-registers.com
Check out the source code on GitHub: https://github.com/hdl-registers/hdl-registers
The following features are supported:
Register fields
Registers can be defined using a TOML/JSON/YAML data file or the Python API. The following code can be generated:
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AXI-Lite register file wrapper using records and native VHDL types for values.
Simulation support packages for compact read/write/wait/checking of register and field values.
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Complete class with setters and getters for registers and fields.
Includes an abstract interface header for unit test mocking.
C header with register addresses and field information.
HTML website with documentation of registers and fields.
Python class with methods to read/write/print each register and field on a target device.
The tool can also be extended by writing your own code generator using a simple but powerful API.
This project is mature and used in many production environments. The maintainers place high focus on quality, with everything having good unit test coverage and a thought-out structure.
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Algorithm | Hash digest | |
---|---|---|
SHA256 | 887bed329d164027f88714e269486ecd1513b0168d566358aabadde0f03f4934 |
|
MD5 | fa28cd8e1cb167ba960900b15e4a1eb3 |
|
BLAKE2b-256 | 5399b27a4e6410e9b197885cf7479b7e92977c6abdfb74b5e0bf5ce586129969 |